Turning to FIG. 11, there is shown a semiconductor device based on complementary metal-oxide semiconductor (CMOS) field-effect transistors manufactured by a generally employed master slice method. The semiconductor device depicted in this Figure is formed by a gate array method on the basis of cells each consisting of two P-channel MOSs and two N-channel MOSs. A static RAM (SRAM) circuit is constructed by employing the semiconductor device described above.
FIG. 12 illustrates a cell 1 on which this semiconductor device is based. In this cell 1, a high concentration N-type diffused layer is formed by introducing an impurity, wherein a mask is a polysilicon gate 14 formed in a P-type well 10 on the semiconductor device. This high concentration N-type diffused layer 15 and the gate electrode 14 constitute two N-channel MOSs (N-MOSs) 11, 12. The gate electrodes 14 of these two N-MOSs 11, 12 are disposed in parallel and have the same orientation. The MOSs 11, 12 share the N-type diffused layer 15 with each other. This region is therefore used in common as a source or drain region. Further, a stopper layer 16, i.e., a high concentration P-type diffused layer, is formed in parallel with these MOSs 11, 12 in a region adjacent to a cell neighboring to the cell 1. This stopper layer 16 is a diffused layer assuming a substantially rectangular shape. The stopper layer is formed for separating the N-MOSs of the adjacent cells and preventing a channel formation when an inter-cell semiconductor surface is inverted. A power supply line is connected via this stopper layer 16 to a substrate, thereby reducing a difference between a substrate potential and a power supply potential. A latch-up of a parasitic transistor formed in the MOS is prevented.
On the other hand, the cell 1 is formed with two P-channel MOSs (P-MOSs) 21, 22 in symmetry with the N-MOSs 11, 12. In association with the P-MOSs 21, 22, as in the case of the N-MOSs 11, 12, a high concentration P-type diffused layer 25 is formed with a polysilicon gate electrode 24 serving as a mask. Owing to this diffused layer 25 and the gate electrode 24, the two P-MOSs 21, 22 are formed in parallel. As in the case of the N-MOSs 11, 12, the P-MOSs 21, 22 share a source or drain region with each other. In association with these P-MOSs 21, 22, for the same purpose as that of the stopper layer 16, a stopper layer 26 is formed of a high concentration N-type diffused layer.
As described above, one basic cell 1 comprises the two N-MOSs 11, 12, the two P-MOSs 21, 22 and stopper layers 16, 26. In the semiconductor device based on the master slice method, the basic cells are continuously formed at constant intervals. Those basic cells are connected with wires of A1 and the like, thus obtaining a desired circuit. The device depicted in FIG. 11 is one example of this arrangement. A SRAM is configured by the gate array method in which designing is effected in conformity with vertical/lateral fixed wiring rules. The following are problems inherent in the conventional complementary semiconductor device in which the P-MOSs and the N-MOSs are continuously formed. Even when a circuit module of a data switch of the above-described SRAM is constructed of unitary elements of N-MOSs, there is no alternative but to use one basic cell in terms of designing the circuit. Taking the wiring rules into consideration, it is difficult to largely change an area of the P-MOS and N-MOS, i.e., a channel width. For this reason, an operating time of the circuit is determined by the P-MOS whose response time is slow.
FIGS. 3 and 4 show a circuit of the SRAM in this embodiment. The SRAM in this embodiment is a 9-element-based logic circuit in which the N-MOS serves as a transmission gate. The transmission gates provided both on the reading side and on the writing side of this circuit are constructed of N-MOSs 41, 42. If the circuit in which the gates are composed of unitary elements of N-MOSs is configured by the conventional complementary semiconductor device given above, as illustrated in FIG. 11, three pieces of basic cells, viz., an area of 12 elements is required for the 9-element-based circuit.
On the other hand, the following relation about the operating time of the semiconductor device is established: EQU tr=4.times.C/(.beta..times.H.times.Vdd) (1)
where tr is the response time indicating a rise or decay time of the MOS, C is the load capacity indicating a capacity of the MOS itself and a capacity of wires parasitic to the MOS, H is the channel width, Vdd is the power supply potential, and .beta. is the current amplification rate per unit length of the MOS. The current amplification rate of the P-MOS is approximately a half or a third the current amplification rate of the N-MOS. Namely, if the channel widths H are substantially equal, the response time tr of the P-MOS is approximately twice or three times as large as that of the N-MOS. For instance, in the conventional complementary semiconductor device, an inverter is composed of the P-MOS and the N-MOS. In this case, because of the channel widths H being equal, a rise time of this inverter is required to be approximately twice or three times the decay time. Hence, in the circuit where a plurality of inverters are connected, the operating time of the device is conditioned by the response time of the P-MOSs.
In the light of such problems, the present invention aims at improving a working efficiency of a semiconductor device by ameliorating a layout of the semiconductor device based on a master slice method in which P-MOSs and N-MOSs are continuously formed and reducing an area occupied by a circuit. It is an object of the present invention to attain a semiconductor device capable of an operating time of a MOS logic circuit by restraining an increase in the area occupied by the circuit.